1. Technical Field
The present disclosure relates to an analog-to-digital (A/D) converter including multiple sub-A/D converters.
2. Description of the Related Art
The A/D converters are widely used in various fields of signal processing, and the important performance indicators of the A/D converters are conversion accuracy and conversion speed. In recent years, along with rapid increase in the speed for wireless communications typified by wireless LANs, mobile phones, millimeter-wave communications, and others, there has been a demand that the A/D converters should achieve both higher conversion accuracy and higher conversion speed. However, the use of a single A/D converter with high accuracy has a limitation on the increase in the speed. For this reason, time interleaving techniques have been recently drawing attention, in which multiple A/D converters are provided in parallel and are configured to sample a signal at sampling timings with phase difference to thereby achieve an increase in the total conversion speed.
An A/D converter in a time-interleaved configuration includes N (an integer of two or more) sub-A/D converters, and achieves the conversion speed N times higher than the conversion speed of each sub-A/D converter. Provided that Fs denotes a conversion frequency of the entire time-interleaved A/D converter, the conversion frequency of each sub-A/D converter is Fs/N.
The time-interleaved configuration, however, is susceptible to mismatches among the sub-A/D converters, such as a DC offset mismatch, a signal gain mismatch indicating a difference in signal gain characteristics, and a sampling timing mismatch. For this reason, the A/D converter in the time-interleaved configuration has a problem in that the characteristics of the A/D converter as a whole are deteriorated due to these mismatches.
The DC offset mismatch occurs, for example, due to offset variations among comparators or amplifiers, or the like. For this reason, the DC offset mismatch causes spurious signals at a frequency of Fs/N*k (k=0 to N) which is not signal-dependent. Then, the signal gain mismatch causes spurious signals at a frequency of Fs/N*k±Fin (k=0 to N). Lastly, the timing mismatch occurs not only due to a difference among clock routing paths and a variation among sampling clock circuits, but also due to variations among input signal routing paths, switch circuits, sampling capacitors, and the like, and causes spurious signals at a frequency of Fs/N*k±Fin (k=0 to N) which is input-dependent.
These spurious signals deteriorate a signal-to-noise plus distortion ratio (SNDR) characteristic of the time-interleaved A/D converter. Among these mismatches, the sampling timing mismatch is problematic, because as the frequency of the input signal becomes higher, the root-square-mean noise in the voltage due to the sampling timing mismatch increases and therefore the conversion accuracy characteristics of the A/D converter are more deteriorated.
Among these mismatches, the DC offset mismatch and the signal gain mismatch have been solved with development of methods in which digital signals converted from analog signals are corrected in a digital domain. Meanwhile, various timing mismatch calibration methods have been studied such as a method of correcting a timing mismatch in the background during execution of signal processing, and a method of correcting a timing mismatch during a calibration time frame provided additionally, while suspending signal processing.
As the method of correcting the timing mismatch during execution of the signal processing, a method has been studied in which a reference A/D converter is provided in addition to the N sub-A/D converters, and is used to correct the timing mismatch, as disclosed in, for example, the specification of U.S. Pat. No. 8,736,470. In the meantime, there is another timing mismatch calibration method in which the timing mismatch is corrected in the digital domain by using only outputs of the A/D converter. Moreover, there is still another method in which the timing mismatch is corrected in an analog domain by giving feedback of a calculation result of the timing mismatch to the phase of each sampling clock, as disclosed in, for example, the specification of U.S. Patent Application Publication No. 2006/0279445.